Low temperature selective growth of silicon or silicon alloys

ABSTRACT

Epitaxial and polycrystalline layers of silicon and silicon-germanium alloys are selectively grown on a semiconductor substrate or wafer by forming over the wafer a thin film masking layer of an oxide of an element selected from scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium; and then growing the epitaxial layer over the wafer at temperatures below 650° C. The epitaxial and polycrystalline layers do not grow on the masking layer. The invention overcomes the problem of forming epitaxial layers at temperatures above 650° C. by providing a lower temperature process.

This application is division of parent application Ser. No. 08/390,132,filed Feb. 17, 1995, (status: pending), which in turn is a divisional ofgrandparent application Ser. No. 08/240,060, filed May 9, 1994, (status:allowed), now U.S. Pat. No. 5,427,630.

FIELD OF THE INVENTION

The present invention relates to semiconductor devices, and moreparticularly, to masking materials for low temperature selective growthof epitaxial layers.

BACKGROUND OF THE INVENTION

Selective epitaxial growth (SEG) of silicon and silicon-germanium alloylayers can be used in both CMOS and bipolar semiconductor devices. Inthe SEG method, the epitaxial layer is selectively grown only on anexposed silicon surface and not on the field area of the device. Thisselective deposition results in a device structure having finedimensional isolation with high aspect ratio geometry and smalleffective channel-width deviation from the design width. As a result,reduction of chip size and area (with CMOS devices) is achieved.

Known methods of selectively growing epitaxial silicon layers involveusing a masking layer, generally silicon dioxide, to prevent growth ofthe epitaxial layer on the field areas. A number of methods are knownfor selectively growing epitaxial silicon with respect to silicondioxide using SiH₂ Cl₂ /HCl or SiCl₄ /H₂ chemistry with eitheratmospheric or low pressure chemical deposition techniques.

In all of the known methods, however, the process temperature for theepitaxial layer deposition is always in the range of 650° to 1100° C.These high temperatures cause problems such as greater stress, siliconwarding, deformation of fine structures, degradation of doping profile,and overall thermal degradation of the semiconductor device. Asunderstood, no such process is presently known for the selective growthof an epitaxial silicon layer at temperatures below 650° C.

SUMMARY OF THE INVENTION

An epitaxial layer is selectively grown on a semiconductor substrate orwafer by forming over the wafer a thin film masking layer of an oxide ofan element selected from the group consisting of scandium, yttrium,lanthanum, cerium, praseodymium, neodymium, samarium, europium,gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium,and lutetium. The epitaxial layer is then grown over the wafer attemperatures below 650° C., but it does not grow on the masking layer.

DESCRIPTION OF THE DRAWINGS

FIGS. 1(a)-1(d) are cross sectional views illustrating selective lowtemperature epitaxial growth on a semiconductor wafer using an exemplarymasking material of the present invention.

FIGS. 2(a)-2(c) are cross sectional views illustrating selective lowtemperature polycrystalline growth on an intermediate layer on asemiconductor wafer using an exemplary masking material of the presentinvention.

FIG. 3 is a cross sectional view illustrating low temperaturepolycrystalline growth on an intermediate layer on a semiconductorwafer.

FIG. 4 is a cross sectional view illustrating low temperature epitaxialgrowth on a semiconductor wafer.

FIG. 5(a) is a Rutherford backscattering spectroscopy (RBS) plot of theexamples illustrated in FIGS. 1(a)-1(d) and 2(a)-2(c). FIG. 5(b) is anRBS plot of the examples illustrated in FIGS. 3 and 4.

FIG. 6(a) is an optical micrograph of the examples illustrated in FIGS.1(a)-1(d), 2(a)-2(c), 3, and 4 after deposition of the epitaxial orpolycrystalline layer. FIG. 6(b) is an optical micrograph of theexamples illustrated in FIGS. 1(a)-1(d), 2(a)-2(c), 3, and 4 after anHCl:H₂ O etch used to remove the masking layer.

DETAILED DESCRIPTION

An exemplary embodiment of the present invention will now be describedmore fully with reference to the accompanying figures, in which growthof an epitaxial layer is illustrated and analyzed. FIGS. 1(a)-1(d) and2(a)-2(c) illustrate the effectiveness of an exemplary masking layeraccording to the present invention to produce selective epitaxial growthat low temperature (below 650° C.) except in FIG. 2 which shows apolycrystalline growth. FIGS. 3 and 4 illustrate low temperaturepolycrystalline growth over an intermediate layer on a semiconductorsubstrate or wafer and epitaxial growth on the semiconductor waferitself. These figures are purely schematic and are not drawn to scale.FIGS. 5(a), 5(b), 6(a), and 6(b) are analyses of the structuresillustrated in the other figures.

An epitaxial layer can be selectively grown on a semiconductor substrateor wafer at low temperature in accordance with an exemplary embodimentof the present invention, in the following manner.

As shown in FIG. 1(a), the starting material is a semiconductorsubstrate or wafer 10. This wafer may be a material such as silicon,silicon carbide, germanium, and compounds and alloys thereof. It will beunderstood that the exact size and shape of the substrate or wafer isnot of critical importance and may be selected to permit the formationthereon of the desired number of circuit elements.

A masking layer 11, e.g. yttrium oxide (Y₂ O₃) is deposited over wafer10 in a desired pattern as shown in FIG. 1(b). The oxide deposition canbe accomplished by known physical vapor deposition techniques such assputtering, or by known chemical vapor deposition techniques, and anydesired pattern can be generated using lithography (optical or e-beam).

An epitaxial layer 12, e.g. silicon, is grown over wafer 10 withpatterned oxide masking layer 11. EDitaxial layer 12 (FIG. 1(c)), whichmay also be a silicon-germanium alloy, is grown by chemical vapor growthtechniques. The deposition is carried out at temperatures below 650° C.U.S. Patent No. 5,298,452, which is assigned to the same assignee asthis application and is incorporated into this application by reference,describes a process for low temperature epitaxial deposition of siliconlayers. A technique such as RBS or optical micrography can be used toconfirm that epitaxial layer 12 does not grow on oxide masking layer 11.Oxide masking layer 11 is then etched off, using for example an HCl:H₂ Osolution, to yield exemplary desired structure 13 as shown in FIG. 1(d).

Oxide masking layer 11 is also an effective masking layer overintermediate layer 14, e.g. a dielectric material such as silicondioxide (SiO₂) or (Si₃ N₄), formed on semiconductor wafer 10, as shownin FIG. 2(a). Intermediate layer 14 can be formed using techniqueswell-known in the art that need not be described in detail.

Oxide masking layer 11, e.g. Y₂ O₃, is patterned over intermediate layer14 according to the same techniques described above. Subsequently, asshown in FIG. 2(b), polycrystalline layer 15, e.g. silicon, is depositedover the structure shown in FIG. 2(a). Although some lateral overgrowthof polycrystalline layer 15 across oxide masking layer 11 is observed,RBS and optical micrography confirm that polycrystalline layer 15 infact grows selectively; that is, it does not grow on oxide masking layer11. Oxide masking layer 11 is then etched off as above to yield thestructure shown in FIG. 2(c).

As shown in FIG. 3, under the same epitaxial deposition conditionsdescribed above, at temperatures below 650° C., polycrystalline layer 15does grow on intermediate layer 14 formed over wafer 10 without maskinglayer 11. Although silicon dioxide acts as a masking material attemperatures above 650° C., at the lower temperature UHV-CVD processinvolved in this invention, polycrystalline growth occurs on the silicondioxide. Similarly, epitaxial layer 12 grows on wafer 10 at theconditions described in this invention, and results in a structure asshown in FIG. 4.

EXAMPLE 1

A 100 nm thick Y₂ O₃ film 11 was deposited on an 82 mm diameter <100> Siwafer 10 (FIG. 1). Y₂ O₃ masking layer 11 was deposited using an MRC 643side scan magnetron sputtering system from a planar oxide magnetrontarget. The base pressure of the MRC sputtering system was between 0.5and 1×10E-7 Torr and the sputtering gas used was 99.9995% pure Ar mixedwith 0.8-1.2% (99,995%) pure O₂. The gas composition was controlled withan optical gas analyzer. The O₂ was used to keep the Y₂ O₃ target frombecoming metallic. A radio frequency power of 1 KW was applied to the Y₂O₃ target giving a deposition rate of 1.33 nm per minute. The Y₂ O₃deposition temperature was kept below 250° C. RBS and XRD confirmed thatY₂ O₃ film 11 was stoichiometric and crystalline.

Silicon wafer 10 with Y₂ O₃ layer 11 was then given an HF dip and placedin an ultra high vacuum chemical vapor deposition (UHV-CVD) reactor forSi and Si₀.9 Ge₀.1 growth. One such reactor is described in U.S. Pat.No. 5,181,964, assigned to the same assignee as this application andincorporated into this application by reference. In the UHV-CVD reactor,the temperature was 550° C.; the pressure was 1 mTorr; the gas was amixture of 100% silane at 1 sccm plus 10% Germane in He at 5 sccm; andthe growth rate was in the range from 10-20 Å per minute and waspracticed at 15 Å per minute. RBS was used to analyze the resultantstructure. The results of this analysis, shown at 20 in FIG. 5(a) ,illustrate that no Si or Si₀.9 Ge₀.1 nucleated and grew on Y₂ O₃ film11. An optical micrograph, 21 in FIG. 6(a) , confirmed the absence ofsilicon on the Y₂ O₃ layer.

EXAMPLE 2

Using the same sputtering system as described above, a 100 nm thick Y₂O₃ film was deposited on an approximately 400 nm thick layer of SiO₂formed by thermal oxidation on silicon wafer 10 (FIG. 2). The resultantstructure was then placed in the UHV-CVD reactor for 140 nm Si₀.9 Ge₀.1growth followed by 100 nm Si growth. The same layer depositionconditions as described above were used in this example. Once again, RBSwas used to analyze the resultant structure. As shown at 30 in FIG. 5(a), no Si or Si₀.9 Ge₀.1 nucleated and grew on the Y₂ O₃ film. An opticalmicrograph confirmed the absence of silicon (with the exception of somelateral overgrowth) as illustrated at 31 in FIG. 6(a) .

EXAMPLE 3

To illustrate the effectiveness of Y₂ O₃ as a masking layer, a blanketSi wafer 10 was used as a control (FIG. 4). No Y₂ O₃ layer was depositedon this substrate. After being given a HF dip, the Si wafer was exposedto UHV-CVD epitaxial growth of 140 nm Si₀.9 Ge₀.1 followed by 100 nm Sigrowth. The conditions for this deposition were the same as thosedescribed in the examples above. RBS was used to determine that Si 100nm thick and Si₀.9 Ge₀.1 140 nm thick in fact nucleated and grew on theSi substrate, as shown at 40 in FIG. 5(b). An optical micrographconfirmed the growth of epitaxial silicon on the silicon as shown at 41in FIG. 6(a).

EXAMPLE 4

As another control, Si wafer 10 with a 400 nm thick layer of SiO₂ 14(FIG. 3) formed thereon was subjected to UHV-CVD deposition ofpolycrystalline Si₀.9 Ge₀.1 and Si growth. The conditions were the samefor this deposition as those described in the examples above. RBS wasused to analyze the resulting structure and determined thatpolycrystalline Si 100 nm thick and Si₀.9 Ge₀.1 140 nm thick did in factnucleate and grow on SiO₂ layer 14. This is illustrated at 50 in FIG.5(b). An optical micrograph confirmed the presence of polycrystallinesilicon over the SiO₂ layer, as shown at 51 in FIG. 6(a).

FIG. 6(b) is an optical micrograph of the above examples 1-4 after thesamples were etched by an HCl:H₂ O mixture. The HCl:H₂ O mixture doesnot etch silicon or silicon dioxide; it only attacks the Y₂ O₃. Thereference numerals in FIG. 6(b) correspond to those in FIG. 6(a) andrefer to the same examples. As can be seen, once the Y₂ O₃ layer wasetched off, at 21 only the original silicon substrate remains while at31, only the SiO₂ layer remains. The fact that the Y₂ O₃ layer was soeasily etched off of the SiO₂ layer at 31 is believed to prove that anypolycrystalline Si that was observed over the Y₂ O₃ layer was lateralovergrowth resulting from the growth of polycrystalline Si on the SiO₂layer. This is because this overgrowth area was easily undercut usingthe etch to remove the Y₂ O₃ and expose the SiO₂.

The above examples were repeated on 125 mm diameter <100> Si andthermally oxidized <100> Si wafers. The same results for each example asreported above were achieved on these substrates.

Because yttrium is a Group IIIB element, and the Group IIIB elements, aswell as the rare earth elements, all exhibit similar properties, it isreasonable to conclude that all Group IIIB oxides and rare earth oxideswill act as a masking material for the selective growth of UHV-CVDepitaxial layers at temperatures below 650° C. The oxides of all ofthese elements are thus within the scope of the present invention, withthe exception of actinium oxide and promethium oxide since actinium andpromethium are radioactive. The following prophetic examples aresubmitted as disclosure of the other elements.

PROPHETIC EXAMPLE 1

Sc₂ O₃ is patterned on a semiconductor substrate for example silicon inaccordance with the sputtering technique described in the aboveexamples. After an HF dip, the wafer with the Sc₂ O₃ masking layer isthen placed in a UHV-CVD reactor for epitaxial 140 nm Si₀.9 Ge₀.1 growthfollowed by 100 nm Si growth under the same conditions as thosedescribed in the above examples. RBS and optical micrographs wouldconfirm that there is no nucleation or growth of epitaxial Si or Si₀.9Ge₀.1 on the Sc₂ O₃ layer.

PROPHETIC EXAMPLE 2

La₂ O₃ is patterned on a semiconductor substrate for example silicon inaccordance with the sputtering technique described in the aboveexamples. After an HF dip, the wafer with the La₂ O₃ masking layer isthen placed in a UHV-CVD reactor for epitaxial 140 nm Si₀.9 Ge₀.1 growthfollowed by 100 nm Si growth under the same conditions as thosedescribed in the above examples. RBS and optical micrographs wouldconfirm that there is no nucleation or growth of epitaxial Si or Si₀.9Ge₀.1 on the La₂ O₃ layer.

PROPHETIC EXAMPLE 3

CeO₂ is patterned on a semiconductor substrate for example silicon inaccordance with the sputtering technique described in the aboveexamples. After an HF dip, the wafer with the CeO₂ masking layer is thenplaced in a UHV-CVD reactor for epitaxial 140 nm Si₀.9 Ge₀.1 growthfollowed by 100 nm Si growth under the same conditions as thosedescribed in the above examples. RBS and optical micrographs wouldconfirm that there is no nucleation or growth of epitaxial Si or Si₀.9Ge₀.1 on the CeO₂ layer.

PROPHETIC EXAMPLE 4

Pr₂ O₃ is patterned on a semiconductor substrate for example silicon inaccordance with the sputtering technique described in the aboveexamples. After an HF dip, the wafer with the Pr₂ O₃ masking layer isthen placed in a UHV-CVD reactor for epitaxial 140 nm Si₀.9 Ge₀.1 growthfollowed by 100 nm Si growth under the same conditions as thosedescribed in the above examples. RBS and optical micrographs wouldconfirm that there is no nucleation or growth of epitaxial Si or Si₀.9Ge₀.1 on the Pr₂ O₃ layer.

PROPHETIC EXAMPLE 5

Nd₂ O₃ is patterned on a semiconductor substrate for example silicon inaccordance with the sputtering technique described in the aboveexamples. After an HF dip, the wafer with the Nd₂ O₃ masking layer isthen placed in a UHV-CVD reactor for epitaxial 140 nm Si₀.9 Ge₀.1 growthfollowed by 100 nm Si growth under the same conditions as thosedescribed in the above examples. RBS and optical micrographs wouldconfirm that there is no nucleation or growth of epitaxial Si or Si₀.9Ge₀.1 on the Nd₂ O₃ layer.

PROPHETIC EXAMPLE 6

Sm₂ O₃ is patterned on a semiconductor substrate for example silicon inaccordance with the sputtering technique described in the aboveexamples. After an HF dip, the wafer with the Sm₂ O₃ masking layer isthen placed in a UHV-CVD reactor for epitaxial 140 nm Si₀.9 Ge₀.1 growthfollowed by 100 nm Si growth under the same conditions as thosedescribed in the above examples. RBS and optical micrographs wouldconfirm that there is no nucleation or growth of epitaxial Si or Si₀.9Ge₀.1 on the Sm₂ O₃ layer.

PROPHETIC EXAMPLE 7

Eu₂ O₃ is patterned on a semiconductor substrate for example silicon inaccordance with the sputtering technique described in the aboveexamples. After an HF dip, the wafer with the Eu₂ O₃ masking layer isthen placed in a UHV-CVD reactor for epitaxial 140 nm Si₀.9 Ge₀.1 growthfollowed by 100 nm Si growth under the same conditions as thosedescribed in the above examples. RBS and optical micrographs wouldconfirm that there is no nucleation or growth of epitaxial Si or Si₀.9Ge₀.1 on the Eu₂ O₃ layer.

PROPHETIC EXAMPLE 8

Gd₂ O₃ is patterned on a semiconductor substrate for example silicon inaccordance with the sputtering technique described in the aboveexamples. After an HF dip, the wafer with the Gd₂ O₃ masking layer isthen placed in a UHV-CVD reactor for epitaxial 140 nm Si₀.9 Ge₀.1 growthfollowed by 100 nm Si growth under the same conditions as thosedescribed in the above examples. RBS and optical micrographs wouldconfirm that there is no nucleation or growth of epitaxial Si or Si₀.9Ge₀.1 on the Gd₂ O₃ layer.

PROPHETIC EXAMPLE 9

Tb₂ O₃ is patterned on a semiconductor substrate for example silicon inaccordance with the sputtering technique described in the aboveexamples. After an HF dip, the wafer with the Tb₂ O₃ masking layer isthen placed in a UHV-CVD reactor for epitaxial 140 nm Si₀.9 Ge₀.1 growthfollowed by 100 nm Si growth under the same conditions as thosedescribed in the above examples. RBS and optical micrographs wouldconfirm that there is no nucleation or growth of epitaxial Si or Si₀.9Ge₀.1 on the Tb₂ O₃ layer.

PROPHETIC EXAMPLE 10

Dy₂ O₃ is patterned on a semiconductor substrate for example silicon inaccordance with the sputtering technique described in the aboveexamples. After an HF dip, the wafer with the Dy₂ O₃ masking layer isthen placed in a UHV-CVD reactor for epitaxial 140 nm Si₀.9 Ge₀.1 growthfollowed by 100 nm Si growth under the same conditions as thosedescribed in the above examples. RBS and optical micrographs wouldconfirm that there is no nucleation or growth of epitaxial Si or Si₀.9Ge₀.1 on the Dy₂ O₃ layer.

PROPHETIC EXAMPLE 11

Ho₂ O₃ is patterned on a semiconductor substrate for example silicon inaccordance with the sputtering technique described in the aboveexamples. After an HF dip, the wafer with the Ho₂ O₃ masking layer isthen placed in a UHV-CVD reactor for epitaxial 140 nm Si₀.9 Ge₀.1 growthfollowed by 100 nm Si growth under the same conditions as thosedescribed in the above examples. RBS and optical micrographs wouldconfirm that there is no nucleation or growth of epitaxial Si or Si₀.9Ge₀.1 on the Ho₂ O₃ layer.

PROPHETIC EXAMPLE 12

Er₂ O₃ is patterned on a semiconductor substrate for example silicon inaccordance with the sputtering technique described in the aboveexamples. After an HF dip, the wafer with the Er₂ O₃ masking layer isthen placed in a UHV-CVD reactor for epitaxial 140 nm Si₀.9 Ge₀.1 growthfollowed by 100 nm Si growth under the same conditions as thosedescribed in the above examples. RBS and optical micrographs wouldconfirm that there is no nucleation or growth of epitaxial Si or Si₀.9Ge₀.1 on the Er₂ O₃ layer.

PROPHETIC EXAMPLE 13

Tm₂ O₃ is patterned on a semiconductor substrate for example silicon inaccordance with the sputtering technique described in the aboveexamples. After an HF dip, the wafer with the Tm₂ O₃ masking layer isthen placed in a UHV-CVD reactor for epitaxial 140 nm Si₀.9 Ge₀.1 growthfollowed by 100 nm Si growth under the same conditions as thosedescribed in the above examples. RBS and optical micrographs wouldconfirm that there is no nucleation or growth of epitaxial Si or Si₀.9Ge₀.1 on the Tm₂ O₃ layer.

PROPHETIC EXAMPLE 14

Yb₂ O₃ is patterned on a semiconductor substrate for example silicon inaccordance with the sputtering technique described in the aboveexamples. After an HF dip, the wafer with the Yb₂ O₃ masking layer isthen placed in a UHV-CVD reactor for epitaxial 140 nm Si₀.9 Ge₀.1 growthfollowed by 100 nm Si growth under the same conditions as thosedescribed in the above examples. RBS and optical micrographs wouldconfirm that there is no nucleation or growth of epitaxial Si or Si₀.9Ge₀.1 on the Yb₂ O₃ layer.

PROPHETIC EXAMPLE 15

Lu₂ O₃ is patterned on a semiconductor substrate for example silicon inaccordance with the sputtering technique described in the aboveexamples. After an HF dip, the wafer with the Lu₂ O₃ masking layer isthen placed in a UHV-CVD reactor for epitaxial 140 nm Si₀.9 Ge₀.1 growthfollowed by 100 nm Si growth under the same conditions as thosedescribed in the above examples. RBS and optical micrographs wouldconfirm that there is no nucleation or growth of epitaxial Si or Si₀.9Ge₀.1 on the Lu₂ O₃ layer.

While this invention has been described in terms of exemplaryembodiments, it is contemplated that it may be practiced as outlinedabove with modifications within the spirit and scope of the appendedclaims.

What is claimed:
 1. A semiconductor device comprising:(a) a substrate; (b) a masking layer formed over a portion of said substrate, creating a masked portion and an unmasked portion of said device, said masking layer being an oxide of an element selected from the group consisting of scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium; and (c) an epitaxial layer selected from the group consisting of silicon and silicon alloys grown over said unmasked portion at a temperature below 650° C.
 2. A semiconductor device as claimed in claim 1, wherein said masking layer is yttrium oxide and said epitaxial layer is silicon.
 3. A semiconductor device as claimed in claim 1, wherein said masking layer is yttrium oxide and said epitaxial layer is a silicon-germanium alloy.
 4. A semiconductor device comprising:(a) a substrate; (b) an intermediate layer formed over said substrate; (c) a masking layer formed over a portion of said intermediate layer, creating a masked portion and an unmasked portion of said device, said masking layer being an oxide of an element selected from the group consisting of scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium; and (d) a polycrystalline layer selected from the group consisting of silicon and silicon alloys grown over said unmasked portion.
 5. A semiconductor device as claimed in claim 4, wherein said intermediate layer is silicon dioxide, said masking layer is yttrium oxide, and said polycrystalline layer is silicon.
 6. A semiconductor device as claimed in claim 4, wherein said intermediate layer is silicon dioxide, said masking layer is yttrium oxide, and said polycrystalline layer is a silicon germanium alloy.
 7. A semiconductor device comprising a substrate and an epitaxial layer selected frown the group consisting of silicon and silicon alloys selectively grown over a portion of said substrate at a temperature below 650° C.
 8. A semiconductor device as claimed in claim 7, wherein said epitaxial layer is silicon.
 9. A semiconductor device as claimed in claim 7, wherein said epitaxial layer is a silicon-germanium alloy.
 10. A semiconductor device comprising a substrate, an intermediate layer formed over said substrate, and a polycrystalline layer selected from the group consisting of silicon and silicon alloys selectively grown over a portion of said intermediate layer at a temperature below 650° C.
 11. A semiconductor device as claimed in claim 11, wherein said intermediate layer is silicon dioxide and said polycrystalline layer is silicon.
 12. A semiconductor device as claimed in claim 11, wherein said intermediate layer is silicon dioxide and said polycrystalline layer is a silicon-germanium alloy. 